Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3e9dc586f5dff34c61782d97df964b75 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-14 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-12044 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-30105 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0214 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-19043 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-19041 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-6835 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-561 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-562 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1203 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-295 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-293 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3114 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-6835 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-568 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06K19-077 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06K19-07 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B42D15-10 |
filingDate |
2009-04-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_91d166669820ca8151de26b2a6cc9de2 |
publicationDate |
2009-10-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
WO-2009131132-A1 |
titleOfInvention |
Semiconductor device and method for manufacturing the same |
abstract |
In a semiconductor integrated circuit sandwiched between a pair of a first impact resistance layer and a second impact resistance layer, an impact diffusion layer is provided between the semiconductor integrated circuit and the second impact resistance layer. By provision of the impact resistance layer against the external stress and the impact diffusion layer for diffusing the impact, force applied to the semiconductor integrated circuit per unit area is reduced, so that the semiconductor integrated circuit is protected. The impact diffusion layer preferably has a low modulus of elasticity and high breaking modulus. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11456187-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10714358-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10804098-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10109500-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10490420-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014346650-A1 |
priorityDate |
2008-04-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |