http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2009078816-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_54851f242fa26ee8e8499a42732d7d3e http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5705e0b6bbf1f826a461c3ccac16513c http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9a49be75c1a725b3215d43e291060e6b |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06513 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-09701 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48463 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-50 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-68 |
| filingDate | 2008-12-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7d01111c12c31a8418654a2e41213c7a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_04b2539cc5815a2020d97ac757da0b13 |
| publicationDate | 2009-06-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2009078816-A1 |
| titleOfInvention | 3d integrated circuit package and method of fabrication thereof |
| abstract | A method of fabricating a 3D integrated circuit structure comprising the steps of: providing a wafer having a plurality of wafer integrated circuits formed thereon, each of said wafer integrated circuits being provided with a plurality of wafer contact elements; providing a plurality of die elements, each of said die elements being configured to be connected electrically to one of said wafer integrated circuits, said die elements each having a plurality of die contact elements; with the die elements at respective predetermined locations on the surface of the wafer the locations of the die contact elements corresponding to locations of said wafer contact elements of the wafer integrated circuits; prvodiing a positioning member in predetermined juxtaposition with said wafer, the positioning member having a plurality of formations at locations of the positioning member corresponding to locations of said plurality of wafer integrated circuits, said formations defining respective sets of lateral boundaries arranged to constrain movement of respective die elements when provided on said wafer such that respective corresponding contact elements of the wafer integrated circuits and die elements are aligned with one another, the method further comprising the step of placing each one of a plurality of die elements on said wafer within one of a set of respective lateral boundaries defined by said formations, and bonding said die elements to said wafer. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8544165-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-101964320-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-102664159-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-102664159-B |
| priorityDate | 2007-12-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 26.