| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4deec2265bd19d89b3f19dd843f62d3b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0aff7e9e05ff47c41090b098bf92188e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4caa77d6ee705e63ba9d4a406c6e5094
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fb091bd111abe07ccea788a8850f6cf1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9afcf4c4a050e6a9f3e3113d10396cd1 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17748
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17796
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-7867
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-8015
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17736 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-173 |
| filingDate |
2008-09-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3bbbf218910428c43067eaf7cb0a6b1e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_14ed0c0e60e0ffdd3d82b2c77c5a85af
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fbcd07be530dfcdb32e8ebb28b16bf30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c205e41cdce42732c0a4840f108e1149 |
| publicationDate |
2009-03-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2009033631-A1 |
| titleOfInvention |
Logic chip, method and computer program for providing a configuration information for a configurable logic chip |
| abstract |
A logic chip comprises a plurality of individually-addressable resource blocks, each comprising logic circuitry. The logic chip also comprises a bus comprising a plurality of bus information lines. A first of the resource blocks comprises a coupling between a first strict sub-set of the bus information lines and the logic circuitry of the first resource block. A second of the resource blocks, which is adjacent to the first resource block, comprises a coupling between a second strict sub-set of the bus information lines and the logic circuitry of the second resource blocks. The first and second sub-sets comprise different bus lines. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9194912-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-106776002-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-106776002-A |
| priorityDate |
2007-09-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |