http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2009012111-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9153f91f54c8309918f02a07e8960f0f http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_78f7080287243c656eebb410f01d1212 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_33b011e77b33662b8bf1f2ff2de7b661 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-1021 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T428-24612 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0277 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76813 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-107 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76807 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-4763 |
| filingDate | 2008-07-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_84e81496724f71210f36e6e130f100f0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fdbd15207f6005066eee708d9a816192 |
| publicationDate | 2009-01-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2009012111-A1 |
| titleOfInvention | Method for fabricating dual damascene profiles using sub pixel-voting lithography and devices made by same |
| abstract | This invention provides processing steps, methods and materials strategies for making patterns of structures for integrated electronic devices and systems. Processing methods of the present invention are capable of making micro- and nano-scale structures, such as Dual Damascene profiles, recessed features and interconnect structures, having non-uniform cross-sectional geometries useful for establishing electrical contact between device components of an electronic device. The present invention provides device fabrication methods and processing strategies using sub pixel-voting lithographic patterning of a single layer of photoresist useful for fabricating and integrating multilevel interconnect structures for high performance electronic or opto-electronic devices, particularly useful for Very Large Scale Integrated (VLSI) and Ultra large Scale Integrated (ULSI) devices. Processing methods of the present invention are complementary to conventional microfabrication and nanofabrication methods for making integrated electronics, and can be effectively integrated into existing photolithographic, etching, and thin film deposition patterning systems, processes and infrastructure. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8620015-B2 |
| priorityDate | 2007-07-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 26.