| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4c153525772cb2a94f93ded9580e72cd
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b035cf97de2b599f6e2d934bf404f19e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4fb8fbe5ff3da7330e0cc5eb98213743 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7843
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823412 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 |
| filingDate |
2008-01-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4a33d8f86366ca798212229789aa3b55
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2b72cd1942dbfc4272eba07c6a52881e |
| publicationDate |
2008-07-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2008087063-A1 |
| titleOfInvention |
Performance enhancement on both nmosfet and pmosfet using self-aligned dual stressed films |
| abstract |
In an integrated circuit comprising both PMOSFETs (200) and NMOSFETs (100), carrier mobility is enhanced on both types of FETs using dual stressed films providing different stresses to the channels of the PMOSFETs (200) and NMOSFETs (100). The adverse impact of having both layers of stressed films along the boundary between different types of films is eliminated by utilizing self-alignment of the edges of a second stressed film (70) to a preexisting edge of a first stressed film (50). At the boundary between the two stressed films (50, 70), one stressed film abuts another but no stressed film overlies another stressed film. By avoiding any overlap of stressed films (50, 70), the stress exerted on the MOSFET channels is maximized. On top the second sressed film (70) has an angled ledge that is self-aligned to the edge of the first stressed film (50). |
| priorityDate |
2007-01-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |