| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_da1eca4375b85213141184827378d49f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0733d72d6f47d7827347aa3aa1a988f3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ccca7ad7a1814082c3bd5d0ed11825da
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8cf8d77ac0eff1767b22d2fb9445b64d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-12044
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T24-44 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23C16-4586
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-70
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-683
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23C16-045
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-67017
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-68714
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-6838
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-677
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-027
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-687 |
| filingDate |
2007-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_52f8131ec9f95ef3dbba7e1f65b1fc57
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_387a0c846dafe30be15b75c2dff1fcc5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bef69a8d214d9fb8996860ce513ebaca |
| publicationDate |
2008-07-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2008079913-A1 |
| titleOfInvention |
Methods, apparatuses, and systems for fabricating three dimensional integrated circuits |
| abstract |
The present invention pertains to methods, apparatuses, and systems for fabricating three-dimensional integrated circuits. One embodiment of the method comprises providing a wafer or other substrate having a plurality of through holes. In addition, the method includes supporting the wafer or other substrate with a wafer or other substrate holder mounted in a process chamber. The method further includes generating a pressure differential between the front side of the wafer or other substrate and the back side of the wafer or other substrate while the wafer or other substrate is supported on the wafer or other substrate holder so that the pressure differential causes fluid flow through the through holes. Also, the method includes establishing process conditions in the process chamber for at least one process to fabricate integrated circuits. Embodiments of a system and embodiments of an apparatus according to the present invention are also presented. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8034409-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-101887863-B |
| priorityDate |
2006-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |