| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_35ea751845d4f12c2327ac42a8223fc9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7853
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7851
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7851
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-053
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-09
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-056
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76232
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76229
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2007-03-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b092f216e7ec71572b7c43d4f6160d9b |
| publicationDate |
2007-09-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2007103147-A2 |
| titleOfInvention |
U-shaped transistor and corresponding manufacturing method |
| abstract |
A method of forming a memory with U-shaped transistors (500) with source/drain regions (502, 504) and channels (506) comprises forming a plurality of parallel deep (400) and shallow (404) trenches in a first substrate region (308) wherein at least one shallow trench is positioned between two deep trenches. A layer of conductive material (454) is deposited over said first region (308) and a second substrate region (310) and is etched to define a plurality of lines (470) separated by gaps over the first region (308) and a plurality of active device elements (460) over the second region (310). Said plurality of lines is removed from said first region to create a plurality of exposed areas (476) into which a plurality of elongated trenches are etched, while the second region (310) is masked. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10515801-B2 |
| priorityDate |
2006-03-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |