| abstract |
The present invention proposes a virtually multi-threaded distributed instruction memory hierarchy that can support the execution of multiple incompatible loops in parallel. In addition to regular loops, irregular loops with conditional constructs and nested loops can be mapped. In the architecture in accordance with embodiments of the present invention, the loop buffers are clustered, each loop buffer having its own local controller, and each local controller is responsible for indexing and regulating accesses to its loop buffer. |