http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2007012102-A2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9cc14caaac3cf1cb128a96ecf7af4f91 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b68312cd343fe9e7287b1acb76e7adc2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e89ea3a0a3823925f2d3b98ba50e6f85 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_81a1bab085ae148268ce12229a7ef5d1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8a088ea5be413d0c8ef4601b3569be10 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2207-7233 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2207-7266 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L2209-046 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-00 |
| filingDate | 2006-07-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4af59146185853493d7ca3c9640a0b9b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bb1c805072b00a134d839b8b5bd983a5 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8a269edab8492b34bfb1a2b7c842b7ec |
| publicationDate | 2007-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2007012102-A2 |
| titleOfInvention | Method and circuit for carrying out calculation operations secure from bugging |
| abstract | The invention relates to a method for carrying out a calculation operation in a digital circuit made up of single-stage logic elements. According to the invention, all single-stage logic elements (2) in the digital circuit (1) carry out a positive or negative monotone function, the digital circuit (1) is alternately switched to a charge phase and an analysis phase, during the charge phase given charge values are applied to the inputs of the digital circuit (3, 4, 5, 6), the inputs and outputs of the single-stage logic elements and therefore also the outputs from the digital circuit (7, 8) are set to given charge values, during the analytical phase, the N masked operands are applied in inverted form and the M masking parameters are applied in inverted form to the inputs of the digital circuit (3, 4, 5, 6), during the analytical phase the 2N operands and the 2 M masking parameters are connected and the logic function ensures for each single-stage logic element (2) during the analytical phase that all logic values occurring at the outputs from the single-stage logic elements are masked according to a masking method. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8213603-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-2228941-A1 |
| priorityDate | 2005-07-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 24.