| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_160059e211982e8daafcdc7c74b997ee |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L7-0054 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0996
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-07 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-093
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-085
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-00 |
| filingDate |
2006-06-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9b6bf366b42f0378d158716afb124d06 |
| publicationDate |
2007-01-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-2007000060-A2 |
| titleOfInvention |
Software controlled clock synthesizer |
| abstract |
An inexpensive high accuracy software controlled clock synthesizer (SCCS) enabling by one order better accuracy of phase & frequency synthesis producing low jitter synchronized clock from external time referencing signals or time referencing messages. The SCCS includes; a hybrid PLL (HPLL) enabling frequency multiplication factors ranging from 1 to 50 000 while maintaining very low output jitter independent of reference clock quality, and noise filtering edge detectors (NFED) enabling by one order better accuracy of referencing signal phase detection. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-116301197-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-116301197-A |
| priorityDate |
2005-06-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |