http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2006078740-A2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1a6c3acd6908494e51ffc1e4b6c9a407 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_57f12cc0f046989f4178e6933d0ba412 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7843 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823842 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 |
| filingDate | 2006-01-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9810a9234ddf07ffcae83c5e7d660930 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6d4449d1f0f0a2a8ad3dd4587a41e391 |
| publicationDate | 2006-07-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2006078740-A2 |
| titleOfInvention | Structure and method to optimize strain in cmosfets |
| abstract | A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N or P) of MOSFET, A strain inducing CA nitride coating having an original full thickness is formed over both the PMOSFETs and the NMOSFETs, wherein the strain inducing coating produces an optimized full strain in one kind of semiconductor device and degrades the performance of the other kind of semiconductor device. The strain inducing CA nitride coating is etched to a reduced thickness over the other kind of semiconductor devices, wherein the reduced thickness of the strain inducing coating relaxes and produces less strain in the other MOSFETs. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2010034488-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2009194053-A |
| priorityDate | 2005-01-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 26.