http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2006040165-A2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36f8253f3d0d59bcd9259217d4385d10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_860899202aefb9d8c158699a1335c6f2 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40117 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-792 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66833 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8246 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2005-10-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9a45d728f2b66abe8c6deef6a4c73cb2 |
| publicationDate | 2006-04-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-2006040165-A2 |
| titleOfInvention | Method for production of charge-trapping memory cells |
| abstract | An oxide layer (2), a nitride layer (3), and a layer of amorphous silicon (4) are applied to a surface of a semiconductor substrate (1). A resist mask (5) is applied and implantations are performed to form doped regions (6) of source and drain and doped regions within the amorphous silicon layer. The resist mask and undoped parts of the amorphous silicon are removed to form a silicon mask (7). The silicon mask is applied to etch back the nitride layer (3). After a removal of the silicon mask (7), the nitride (3) is oxidized to form an oxide-nitride-oxide layer sequence which is laterally restricted to the area above the source/drain regions (6). |
| priorityDate | 2004-10-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 26.