| abstract |
A non-volatile semiconductor storage device array organization for wide program operations is achieved. The device comprises a memory cell array region in which a plurality of C columns and R rows of memory cells comprise one UNIT, arranged in a 'diffusion bit' array organization which is comprised of R rows of word lines running in a first direction, and C columns of diffusion sub bit lines running in a second direction, and C columns of sub control gate lines running in the same second direction and a sense amplifier/ page buffer area (134) shared by several UNIT'S through a bit decode circuit (70, 71, 72), wherein the diffusion sub bit lines in each of the UNIT'S are connected to main bit lines (MBL) which are in turn connected to the sense amplifier / page buffer area, wherein the bit decode circuit (70, 71, 72) selects one diffusion sub bit line column of memory cells in every E columns. |