http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-0250895-A2

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-288
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
filingDate 2001-10-23-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_63eaab1acff6cebfc49c480056dbbcaf
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publicationDate 2002-06-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber WO-0250895-A2
titleOfInvention Controlled anneal conductors for integrated circuit interconnects
abstract A method is provided for manufacturing an integrated circuit on a semiconductor wafer (200) having a semiconductor substrate with a semiconductor device thereon. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier (226, 232) layer is deposited to line the opening. A seed layer (228, 234) is deposited on the barrier layer and securely bonds to the barrier layer. A conductor (230, 236) layer is deposited to fill the channel opening over the barrier layer. A planarization technique is used to planarize the barrier, seed layer, and conductor layers to be coplanar with the dielectric layer to form a conductor channel. The semiconductor wafer is then subjected to a two step timed anneal.
priorityDate 2000-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 26.