http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-02086947-A3
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36f8253f3d0d59bcd9259217d4385d10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3212 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-75 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76838 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-60 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-321 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-52 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04 |
| filingDate | 2002-04-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9d159a36b655901adfa5d7d031c8398b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ffb142e27ee47550d3bd4a5814f58e9e |
| publicationDate | 2003-12-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | WO-02086947-A3 |
| titleOfInvention | A method for making a metal-insulator-metal capacitor using plate-through mask techniques |
| abstract | A method for making a metal-insulator-metal capacitive structure includes depositing a copper barrier and seed layer over a support structure such as an inter-level dielectric layer, forming a dielectric over the copper barrier and seed layer, and then forming a forming a metal layer over the dielectric. The copper barrier and seed layer forms a bottom plate of a capacitor, and the metal layer forms the upper plate which is separated from the bottom plate by the dielectric. By forming the bottom plate from a copper barrier and seed layer, reduced sheet resistance and surface roughness is achieved, both of which enhance the performance of the capacitor. This performance is further enhanced by forming the capacitor to have a damascene structure. Preferably, at least one conductive interconnect is formed simultaneously with the formation of the capacitor. This is made possible, at least in part, by forming the interconnect using a plate-through mask technique. The interconnect and capacitor are then finished using one and only one planarizing (e.g., CMP) step. The result is to form a capacitor and interconnect structure in far fewer steps than conventionally required, which translates into improved cost and efficiency. |
| priorityDate | 2001-04-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 26.