http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-02058241-A2

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filingDate 2001-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d591094abbbf5cfcd9e9396309c0523d
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publicationDate 2002-07-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber WO-02058241-A2
titleOfInvention Method for conditioning semiconductor-on-insulator transsistors in programmable logic devices
abstract Method preconditioning and in-use conditioning of transistors formed on a semiconductor-on-insulator structue is described. More particularly, transistors of a programmable logic device (PLD), such as a field programmable gate array (FPGA), are preconditioned to take advantage of charge accumulation owing to a 'floating body' effect. This preconditioning takes a form of switching transistors on and off prior to customer operation. Accordingly, semiconductor-on-insulator transistors accumulate charge during this switching period, so when customer operation takes place, transistor switching times are less variable over a period of operation of the PLD. Additionally, a design process and implementation is described for identification and in-use conditioning of transistors that may need conditioning during customer operation to control switching time variability.
priorityDate 2001-01-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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