| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_21c03b8b989cf6fdabfde44102e84a2d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ce4a8fa1edb7f16cef3e58ec564959a9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d27d4a888493599e37ed462796f5a2b7 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30076
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3004
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30127
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3824
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-8015
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3851
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3012
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3842
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3834 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-80
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-38
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-30 |
| filingDate |
2000-08-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_34b3716d285b2a6a28b6cca13f246c22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_befb805f1c1686fddca6489cd488646c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_95fc64fc5b3eba9711348f0553795f28 |
| publicationDate |
2001-03-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
WO-0116782-A2 |
| titleOfInvention |
Parallel processor architecture |
| abstract |
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write reference. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1979808-A4
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2007092528-A2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-2154607-A3
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8984256-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/AU-2007212342-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/AU-2008355072-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/AU-2008355072-C1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9824038-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9824037-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9830284-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9128818-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9830285-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1979808-A2 |
| priorityDate |
1999-08-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |