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publicationDate 2002-09-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber WO-0116769-A9
titleOfInvention Sram controller for parallel processor architecture
abstract A controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.
priorityDate 1999-08-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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