| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9047b16961c0aee78d7de367969339b2 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-1202 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-028
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11582
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11578
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-12 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11582
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11578 |
| filingDate |
2016-02-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-02-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_98962d7a569b930bf84eb5a1096c2e97
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_56a7d76955b8d6599929ddff73b24fe5 |
| publicationDate |
2020-02-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-RE47866-E |
| titleOfInvention |
Three-dimensionally stacked nonvolatile semiconductor memory |
| abstract |
A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal. |
| priorityDate |
2008-10-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |