http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-RE46754-E
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_7e18df6b8ebc657114a3e5b7b3cdffb2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-222 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 |
| filingDate | 2014-12-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2018-03-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_146684d28467bdb2de2aa8e209aef4f0 |
| publicationDate | 2018-03-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-RE46754-E |
| titleOfInvention | Integrated circuit for clock generation for memory devices |
| abstract | A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK 1 ) having a first clock frequency to generate a second clock signal (CLK 20 ) having a second clock frequency which is an integer multiple of the first clock frequency. A shift register (SH) receives the second clock signal as a data input signal, and comprises a plurality flip-flops having clock inputs coupled to receive the first clock signal (CLK 1 ), and further coupled so that the data output of a preceding flip-flop is coupled to be the data input of a following flip-flop. The second clock signal is shifted through the shift register (SH) in response to the first clock signal (CLK 1 ) to generate a plurality of shifted clock signals (CLK 21, . . . , CLK 32 ) at respective data outputs of the plurality of flip-flops. A multiplexer commonly coupled to the data outputs of the flip-flops selects one of the shifted clock signals (CLK 21, . . . , CLK 32 ) to serve as an output clock signal for transmission of the buffered data to a memory device. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018005697-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10651836-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10490281-B2 |
| priorityDate | 2007-04-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 47.