| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C19-28 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-1778
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7851
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-0013
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C19-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-124
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1255 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C19-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-177
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-00 |
| filingDate |
2017-05-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2018-06-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_598e7504717c4325e148358d866e9309
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d524ca6c4608c94abe01f7f8c1c8ebbc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aa07e0c99c24a951a9ae29a1ca0eb12f |
| publicationDate |
2018-06-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9998119-B2 |
| titleOfInvention |
Semiconductor device, electronic component, and electronic device |
| abstract |
Provided is a semiconductor device in which leakage current due to miniaturization of a semiconductor element is reduced and delay at a time of context switch of a multi-context PLD is reduced. A first transistor and a second transistor included in a charge retention circuit functioning as a configuration memory each include an oxide semiconductor in a semiconductor layer serving as a channel formation region. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. One of a source and a drain of the second transistor is connected to a switch for context switch. In the switch used for context switch, electrostatic capacitance on an input side to which the one of the source and the drain of the second transistor is connected is larger than electrostatic capacitance on an output side. |
| priorityDate |
2016-05-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |