http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9983257-B2

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filingDate 2015-10-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2018-05-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c773aeee3aea997662f5af041d750eb6
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publicationDate 2018-05-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-9983257-B2
titleOfInvention Test line patterns in split-gate flash technology
abstract The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed. The integrated chip has a semiconductor substrate. A test line letter is arranged over the semiconductor substrate. The test line letter comprises a positive relief that protrudes outward from the semiconductor substrate in the shape of an alpha-numeric character. One or more dummy structures are arranged over the semiconductor substrate. The one or more dummy structures are proximate to a boundary of the test line letter.
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