http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9941870-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1066 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K2005-00052 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4093 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4076 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-134 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1093 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4093 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4076 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-134 |
| filingDate | 2015-09-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2018-04-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4dc7f17301ec3a14baaaa32053d6dedd http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5b846d42fec9e2888d65444b88efa3ed |
| publicationDate | 2018-04-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-9941870-B2 |
| titleOfInvention | Adjustable delay circuit for optimizing timing margin |
| abstract | The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal line, an output circuit, and a plurality of delay circuits. Each of the plurality of delay circuits may be configured to provide respective delay amounts that are different from each other, and where a first one of the plurality of delay circuits, which may be arranged most adjacently to the output circuit, being smaller in delay amount than other ones of the plurality of delay circuits. Each of the plurality of delay circuits may include an input node and an output node, and a selected one of the plurality of delay circuits connected at its input node to the signal line and at its output node to the output circuit, the rest of the plurality of delay circuits being disconnected from the signal line and the output circuit. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10218340-B2 |
| priorityDate | 2015-09-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID7156993 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID426135032 |
Total number of triples: 25.