| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76804 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-522
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522 |
| filingDate |
2016-08-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2018-04-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f6d36fe877faa19e5ef307cc914bd411
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_383cb5c720fe88ddcf9ee6e6dcdb2872
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0a7f256c20b8adb38be2625b080c6d90
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e4478da2ff73a422a5bc1f0108d4b6c5 |
| publicationDate |
2018-04-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9941172-B2 |
| titleOfInvention |
Method for fabricating semiconductor device including a via hole in a mask pattern |
| abstract |
A method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes forming an interlayer insulating layer that comprises a first region and a second region, forming an etch stop pattern for exposing the second region in the first region of the interlayer insulating layer and forming a mask pattern that comprises a first via-hole that exposes an upper surface of the etch stop pattern and a second via-hole that penetrates the interlayer insulating layer on the interlayer insulating layer and the etch stop pattern. |
| priorityDate |
2015-09-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |