| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f56b5174f7d196258707ccf1d609796e |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10897
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10894
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823443
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10808
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10852
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-315
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-09
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-31 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L49-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 |
| filingDate |
2013-04-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2018-03-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f2ae73d1e1a17ecd092e744f25fca049
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_20824ab6a73109a07f0d31699b6ec7e5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_320e7234c86a9ddcef83e408b1ddf8c1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_039dc6d81d6c11b0cfcd254bf3f66b8b |
| publicationDate |
2018-03-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9917083-B2 |
| titleOfInvention |
Semiconductor device with an upper surface of a substrate at different levels and method of manufacturing the same |
| abstract |
A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11177285-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10734410-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018076220-A1 |
| priorityDate |
2012-04-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |