| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b6e4b1c02022f81d8cdc1426cdf55ebf |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-4402 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0408
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-56
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-028
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-005 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C5-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-26 |
| filingDate |
2017-01-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2018-02-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6e69254e80c5520d7eac12f89aaf56cc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_680a2b60a85ce2068b5b4b07f10877b6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_89697dd651fda366e3e0cf148a980e62 |
| publicationDate |
2018-02-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9892794-B2 |
| titleOfInvention |
Method and apparatus with program suspend using test mode |
| abstract |
A nonvolatile memory controller is disclosed that includes a read circuit configured to read memory cells of a nonvolatile memory device and a program and erase circuit configured to program and erase memory cells of the nonvolatile memory device. The nonvolatile memory controller includes a NAND shared algorithm circuit configured to communicate with the nonvolatile memory device so as to enter a test mode of the nonvolatile memory device and configured to modify the trim registers while the nonvolatile memory device is in the test mode such that the nonvolatile memory device performs one or more operations. The operations may include a suspendable program operation, a program suspend operation and an erase suspend operation. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11514992-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11514994-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10061512-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10978166-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10573397-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11699493-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11663076-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018101302-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11164645-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11086716-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11398291-B2 |
| priorityDate |
2016-01-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |