| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ab25b307cada42e5d8f8afb672b8c7c3 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-174
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-1024
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-7208
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-263 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L67-1097
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C14-0045
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-382
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0246
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C14-0018
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-4009
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0868 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C13-00 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-0868
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C14-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-38
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L29-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-02 |
| filingDate |
2015-03-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2018-02-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_35c178154b45eeab60d16ff82efd18fd
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8bf78d3f995358e8f136b20679d11cf1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ec02240e21f466dde096e94c306b1be5 |
| publicationDate |
2018-02-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9887008-B2 |
| titleOfInvention |
DDR4-SSD dual-port DIMM device |
| abstract |
As a solution to the type of problems noted above, this disclosure provides novel methods and systems that include dual-port solid-state drive (SSD) DIMM devices to provide primary storage capabilities with very low latency and better availability of DDR4 devices. The dual-port DDR4-SSD flash memory devices guarantee primary storage devices still accessible with one CPU or network failure. The novel DDR4 memory bus devices may be used not only for memory media and storage device buffers, but also to allow two CPUs to share data stored in flash SSD chips and to greatly improve DDR4 bus efficiency and bus utilizations by block accesses and eliminate PCIE-DMA data transfers. Through the features of the claimed subject matter described herein, dual-port DDR4-DIMM memory devices can be achieved that provide an All-Flash-Array storage system with substantially higher reliability, availability, and performance over conventional SATA/SAS-SSD, PCIE-SSD, and NVME-SSD solutions. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11409684-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11119676-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11157356-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10649927-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11625341-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11631443-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019108145-A1 |
| priorityDate |
2014-03-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |