| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66628
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-167 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-165 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-167 |
| filingDate |
2014-03-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2017-11-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bf637865a4bd4a5706b47ab5bfb72c7c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a429583e6e2138bc567dc679920c68da
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5c05e502edf330b56b04d521c9c0ccb1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_899644a05f72901f0fba78f70fc59990
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_492a0f91a813e784069d46fa1ad293b2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4a9ca78749a8074e24f2a311396b0be5 |
| publicationDate |
2017-11-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9812569-B2 |
| titleOfInvention |
Semiconductor device and fabricating method thereof |
| abstract |
A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10636909-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10056455-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10879396-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11575009-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019157425-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10164100-B2 |
| priorityDate |
2014-01-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |