| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B2201-0292
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C2201-0132
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B2201-0271
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B2201-0242
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B2203-0109
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B2201-0235
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B2201-0264 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C1-00801
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B7-007
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C1-00357
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C1-00595 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B81C1-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B81B7-00 |
| filingDate |
2015-04-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2017-08-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f08b0ee57da2fc8885f52c176617990e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_100bea405feb0f1b254205de79b4b918
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c0e6f6a52be3735dca7c3ca042d88c1b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_104481a28ebeff17d9d05cc6f29522b7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_89da8ca6c4f4e2faad523572087e24e8 |
| publicationDate |
2017-08-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9738516-B2 |
| titleOfInvention |
Structure to reduce backside silicon damage |
| abstract |
A method of forming an IC (integrated circuit) device is provided. The method includes receiving a first wafer including a first substrate and including a plasma-reflecting layer disposed on an upper surface thereof. The plasma-reflecting layer is configured to reflect a plasma therefrom. A dielectric protection layer is formed on a lower surface of a second wafer, wherein the second wafer includes a second substrate. The second wafer is bonded to the first wafer, such that a cavity is formed between the plasma-reflecting layer and the dielectric protection layer. An etch process is performed with the plasma to form an opening extending from an upper surface of the second wafer and through the dielectric protection layer into the cavity. A resulting structure of the above method is also provided. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10273143-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10870574-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11365115-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018134542-A1 |
| priorityDate |
2015-04-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |