| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d869049b035b5f98c72188a4cf14c6fc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_31e38a0807288c5206cbc1af64d68cf6 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-23 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-146
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-101
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-143
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-08 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-23 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-14 |
| filingDate |
2015-01-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2017-06-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d9c648e229ba766501dead6511dda526
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7e8363307da1cb34214156790a8eedb5 |
| publicationDate |
2017-06-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9692427-B2 |
| titleOfInvention |
Apparatus and methods for phase-locked loops with soft transition from holdover to reacquiring phase lock |
| abstract |
Provided herein are apparatus and methods for phase-locked loops (PLLs). In certain configurations, a clock system includes a PLL, a control circuit, and a holdover circuit that is electrically coupled to an input of the PLL's loop filter via a holdover switch and a variable resistor. The control circuit generates an input clock signal for the PLL based on a selected reference clock signal. When the control circuit determines that the selected reference clock signal is unreliable, the control circuit disables the PLL's feedback loop and turns on the holdover switch. After the selected reference clock signal is changed or otherwise becomes reliable, the control circuit enables the PLL's feedback loop while keeping the holdover switch turned on, and controls a resistance of the variable resistor over time to provide a soft transition from holdover to reacquiring phase lock. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11177815-B2 |
| priorityDate |
2014-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |