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filingDate 2014-07-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2017-05-23-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3219c79a1169bf81630f16f094b28ad9
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publicationDate 2017-05-23-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-9659831-B2
titleOfInvention Methods and structures for detecting low strength in an interlayer dielectric structure
abstract A method for manufacturing a semiconductor device is disclosed. The method includes generating a thermo-mechanical stress within a plurality of layers of a wafer, and after generating the thermo-mechanical stress, testing an interfacial strength level associated with one or more of the plurality of layers.
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Total number of triples: 27.