| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ba57d75dbee0bd9af31a93f057d55d2d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2213-0026 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-4022
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-4282
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F17-30985
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F16-90344
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0655
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0688
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-061 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F17-30 |
| filingDate |
2015-01-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2017-05-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7134eb1970adcfe6536c4a90f7b5c233
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_67cfdb236ebf80e16f95fbad28d884e5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2f42abf0e7de3e086f867751074a4952 |
| publicationDate |
2017-05-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9658977-B2 |
| titleOfInvention |
High speed, parallel configuration of multiple field programmable gate arrays |
| abstract |
Representative embodiments are disclosed for a rapid and highly parallel configuration process for field programmable gate arrays (FPGAs). In a representative method embodiment, using a host processor, a first configuration bit image for an application is stored in a host memory; one of more FPGAs are configured with a communication functionality such as PCIe using a second configuration bit image stored in a nonvolatile memory; a message is transmitted by the host processor to the FPGAs, usually via PCIe lines, with the message comprising a memory address and also a file size of the first configuration bit image in the host memory; using a DMA engine, each FPGA obtains the first configuration bit image from the host memory and is then configured using the first configuration bit image. Primary FPGAs may further transmit the first configuration bit image to additional, secondary FPGAs, such as via JTAG lines, for their configuration. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11461043-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10817214-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11474714-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11316733-B1 |
| priorityDate |
2013-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |