| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_82a9e22a923eca64a02a97f0dfb493ed |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7851
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-94
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0629
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66181
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0716 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L49-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-94
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-07 |
| filingDate |
2016-03-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2017-04-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4752079ee4e5886e5ea49e3be627a4a8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6c660261a85716216bb3b0639f25d189
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_790dfd1a153743df97a6de29970d63cf
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ab4d6fad0202c20ee49cc9c2f38c8bc6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_46d4e46120d1dbe6e95ba0d71da1091f |
| publicationDate |
2017-04-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9633996-B1 |
| titleOfInvention |
High density area efficient thin-oxide decoupling capacitor using conductive gate resistor |
| abstract |
A semiconductor device arranged between a source voltage (Vss) and a power voltage (Vdd) may include a first terminal coupled to the power voltage Vdd. The semiconductor device may also include a decoupling capacitor. The decoupling capacitor may include a semiconductor fin coupled to the first terminal, a dielectric layer on the semiconductor fin, and a gate on the dielectric layer. The semiconductor device may further include a second terminal. The second terminal may include a conductive gate resistor coupled in series with the gate of the decoupling capacitor. The second terminal may be coupled to the source voltage Vss via a first interconnect layer (M1). |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10505541-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019058477-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2019070346-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111183516-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021288137-A1 |
| priorityDate |
2016-03-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |