http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9581645-B2

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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-319
filingDate 2014-02-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2017-02-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c9c993a5160dcff965de225ec29a1f0f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_da2bf950f41534983945f4475bbd2d34
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publicationDate 2017-02-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-9581645-B2
titleOfInvention Test circuit providing different levels of concurrency among radio cores
abstract A testable integrated circuit chip ( 80, 100 ) includes a functional circuit ( 80 ) having modules (IP.i), a storage circuit ( 110 ) operable to hold a table representing sets of compatible tests that are compatible for concurrence, and an on-chip test controller ( 140, 150 ) coupled with the storage circuit ( 110 ) and with the functional circuit modules (IP.i. The test controller ( 140, 150 ) is operable to dynamically schedule and trigger the tests in those sets, which promotes concurrent execution of tests in the functional circuit modules (IP.i). Other circuits, wireless chips, systems, and processes of operation and processes of manufacture are disclosed.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11538543-B2
priorityDate 2011-01-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 23.