| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bbdc68ca0aa38fef2d059853ef2b31e6 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41758 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66522
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7787
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66484
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7831
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-2003 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-338
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-778 |
| filingDate |
2016-04-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2017-01-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e411186c05b58b3d0329d846f976d76f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_08b5fe1252e28c3a6029bedbd9ac19a4 |
| publicationDate |
2017-01-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9543425-B2 |
| titleOfInvention |
Multi-finger large periphery AlInN/AlN/GaN metal-oxide-semiconductor heterostructure field effect transistors on sapphire substrate |
| abstract |
MOSHFET devices are provided, along with their methods of fabrication. The MOSHFET device can include a substrate; a multilayer stack on the substrate; a ultra-thin barrier layer on the multilayer stack, wherein the ultra-thin barrier layer has a thickness of about 0.5 nm to about 10 nm; a dielectric, discontinuous thin film layer on portions of the ultra-thin barrier layer, wherein the dielectric, discontinuous thin film layer comprises SiO 2 ; a plurality of source electrodes and drain electrodes formed directly on the ultra-thin barrier layer in an alternating pattern such that the dielectric, discontinuous thin film layer is positioned between adjacent source electrodes and drain electrodes; a plurality of gate electrodes on the dielectric, discontinuous thin film layer; and a gate interconnect electrically connecting the plurality of gate electrodes. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11021789-B2 |
| priorityDate |
2014-03-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |