| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_58ded8a2e72c4afb0037e16977f0fb19
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d435b19f6d79b3d1b956be35529aa950
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fba5536ba1e026b3d50352dc50f216e7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-222
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B61-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L43-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L43-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L43-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-01
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-80
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-228
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B61-22 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L43-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L43-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L43-08 |
| filingDate |
2015-07-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2017-01-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_848538d4c51d1f7e4898546513bc2e93
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e1958a12dbd5666865e058ebab12e27f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_285045cca422a13570db6d95165c5374 |
| publicationDate |
2017-01-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9543357-B2 |
| titleOfInvention |
Magnetoresistive random access memory devices and methods of manufacturing the same |
| abstract |
An MRAM device comprises an insulating interlayer comprising a flat first upper surface on a first region and a second region of a substrate. A pattern structure comprising pillar-shaped magnetic tunnel junction (MTJ) structures and a filling layer pattern between the MTJ structures is formed on the insulating interlayer of the first region. The pattern structure comprises a flat second upper surface that is higher than the first upper surface. Bit lines are formed on the pattern structure that contact top surfaces of the MTJ structures. An etch-stop layer is formed on the pattern structure between the bit lines of the first region and the first upper surface of the first insulating interlayer of the second region. A first portion of an upper surface of the etch-stop layer on the first region is higher than a second portion of the upper surface of the etch-stop layer on the second region. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10636465-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11462584-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10804320-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10504902-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10497857-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10504959-B2 |
| priorityDate |
2014-07-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |