Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_88fc7f9eb617072238851d46591a0c76 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76883 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-283 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-70 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-283 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 |
filingDate |
2015-09-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2017-01-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dedbdd67f4e7ed0b100f00c1ada6cb87 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dbffbe577124483d0c4cd4aa63d17178 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3a048d03ef79453f31ebf5c3868f4dcc http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f67ef8ccd3f96c624ef8625102a76fdb http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_52437fccfe860070cb7892f33c866b2e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_639ae78ec6266ada61a0573e09ef13be http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_634c42135803a65dd37f239cc708f5a1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_781017325760945d229f4fb7a347e117 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_037612964a09b745c0cc8b4baa99fa45 |
publicationDate |
2017-01-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-9543211-B1 |
titleOfInvention |
Semiconductor structure and manufacturing method thereof |
abstract |
A manufacturing method of a semiconductor structure includes the following steps. Gate structures are formed on a semiconductor substrate. A source/drain contact is formed between two adjacent gate structures. The source/drain contact is recessed by a recessing process. A top surface of the source/drain contact is lower than a top surface of the gate structure after the recessing process. A stop layer is formed on the gate structures and the source/drain contact after the recessing process. A top surface of the stop layer on the source/drain contact is lower than the top surface of the gate structure. A semiconductor structure includes the semiconductor substrate, the gate structures, a gate contact structure, and the source/drain contact. The source/drain contact is disposed between two adjacent gate structures, and the top surface of the source/drain contact is lower than the top surface of the gate structure. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11610823-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11251306-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109698166-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11037834-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10943822-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11757040-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019393098-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109698166-B http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10529624-B2 |
priorityDate |
2015-08-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |