| abstract |
A semiconductor device includes a contact region over a substrate. The semiconductor device further includes a metal pad over the contact region. Additionally, the semiconductor device includes a post passivation interconnect (PPI) line over the metal pad, where the PPI line is in contact with the metal pad. Furthermore, the semiconductor device includes an under-bump-metallurgy (UBM) layer over the PPI line. Moreover, the semiconductor device includes a plurality of solder balls over the UBM layer, the plurality of solder balls being arranged at some, but not all, intersections of a number of columns and rows of a ball pattern. |