| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_459ed213007307f4e4bee9a68a346ca7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B2201-0264
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-1063
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C2201-0132
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B2207-07 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-475
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53219
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53233
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B7-007
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C1-00849
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C1-00095
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02068
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C1-00396 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-44
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B81C1-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-475 |
| filingDate |
2015-01-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2016-08-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_95b0d94bc4ce2391a675295c2f44f631
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_152102eca7ba1e217d7b36b7376e474c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_279c9ddb534cfa47c81405c2566818c0 |
| publicationDate |
2016-08-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9416004-B2 |
| titleOfInvention |
Semiconductor device and fabrication method |
| abstract |
Semiconductor devices and fabrication methods are provided. In a semiconductor device, a semiconductor substrate includes a first electrode layer having a top surface coplanar with a top surface of the semiconductor substrate. A sacrificial layer is formed on the semiconductor substrate and the first electrode layer. A first mask layer made of a conductive material is formed on the sacrificial layer. The first mask layer and the sacrificial layer are etched until a surface of the first electrode layer is exposed to form openings through the first mask layer and the sacrificial layer. A cleaning process is performed to remove etch byproducts adhered to a surface of the first mask layer and adhered to sidewalls and bottom surfaces of the openings. Conductive plugs are formed in the openings after the cleaning process. |
| priorityDate |
2014-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |