| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76805
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76802
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0805
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-60
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5223 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L49-02 |
| filingDate |
2014-04-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2016-06-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_508cff4b453cb01bce10fe0879aa1b53
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a97531cf3ce34f46306a2ef7aec42ec7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5d22d4d6bc70e315a5a09762adc4958a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_37e633896135ef7e70fa2f521b530017
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6423476d0b7ef76a27e3e688580343c9 |
| publicationDate |
2016-06-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9368392-B2 |
| titleOfInvention |
MIM capacitor structure |
| abstract |
The present disclosure relates to a MIM (metal-insulator-metal) capacitor, and an associated method of formation. In some embodiments, the MIM capacitor includes a first electrode having a capacitor bottom metal layer disposed over a dielectric buffer layer located over an under-metal layer. A capacitor dielectric layer is disposed onto and in direct contact with the capacitor bottom metal layer. A second electrode having a top capacitor metal layer is disposed onto and in direct contact with the capacitor dielectric layer. A capacitor inter-level dielectric (ILD) layer is disposed over the top capacitor metal layer, and a substantially planar etch stop layer disposed over the capacitor ILD layer. The capacitor's simple stack provides for a small step size that prevents topography related issues, while the dielectric buffer layer removes design restrictions on the lower metal layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11031457-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10886362-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10290700-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11121266-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10319521-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9966425-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I746455-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9773860-B1 |
| priorityDate |
2014-04-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |