http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9349662-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-34 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-30 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-66 |
| filingDate | 2012-12-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2016-05-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_00033b9958bc8d263edcf773e5ccd963 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4f7d4aabb66946204e999c3232c8ba7d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3a7d10e3c113cf046a4ca84ddd40205a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d03d7867bf0ec3ee01792e1462b2994e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c97f6f8e8a5770b0e63be7ae6a84659f |
| publicationDate | 2016-05-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-9349662-B2 |
| titleOfInvention | Test structure placement on a semiconductor wafer |
| abstract | A method of fabricating integrated circuit devices is provided. The method includes forming a plurality of spaced integrated circuit dies on a semiconductor wafer and forming a dedicated test die on the semiconductor wafer adjacent the plurality of spaced integrated circuit dies, the dedicated test die including a test structure having a first width when viewed in a top view and being operable to generate wafer evaluation data. Further, the method includes forming a scribe line region interposed between the plurality of spaced integrated circuit dies, the scribe line region having a second width defined by a distance between adjacent integrated circuit dies when viewed in a top view, the second width being smaller than the first width, and the scribe line region being free of test structures. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11467207-B2 |
| priorityDate | 2012-12-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 27.