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filingDate 2014-05-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2016-05-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9c0014e99666f3c48d80b26ecaf71590
publicationDate 2016-05-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-9348961-B2
titleOfInvention Logic analyzer circuit for programmable logic device
abstract The present disclosure relates to methods and related systems and computer-readable mediums. The methods include receiving a design for a programmable logic device (PLD). The design includes a plurality of nodes. The method also includes modifying, via one or more hardware processors, the design to include a logic analyzer circuit. The logic analyzer circuit includes inputs for a plurality of selectable groups of capture signals for connecting to selected nodes of the plurality of nodes. In addition, the method includes outputting the design to the PLD to program the PLD. The disclosure also relates a system comprising a user logic circuit, a logic analyzer circuit, and a memory.
priorityDate 2014-03-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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