| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_81851e105df9f5a9ad2b0a7c2783bcc0 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11573
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40117
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28282
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 |
| filingDate |
2013-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2015-07-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0fccd3d8f7fcbef7bc60380caed0bdfb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_26fb889a505657f6f254d7b2e4f06995
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_57b032a1dc03c4ce05aa5d0d6eb0db3c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6b45eb97a4e3904d0bb9e5e6a41cfc32 |
| publicationDate |
2015-07-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9082867-B2 |
| titleOfInvention |
Embedded cost-efficient SONOS non-volatile memory |
| abstract |
A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell for use in a CMOS IC, where the CEONOS NVM cell requires two or three additional masks, but is otherwise substantially formed using the same standard CMOS flow processes used to form NMOS transistors. The cell is similar to an NMOS cell but includes an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data. The cells utilize special source/drain engineering to include pocket implants and lightly-doped drain extensions, which facilitate program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share a drain diffusion and three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI). |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11653503-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10763305-B2 |
| priorityDate |
2013-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |