| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bf83328d853bc7476ca10212837b3a01 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0878
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66689
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1087 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-402
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-01
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7816 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K3-01
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 |
| filingDate |
2013-04-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2015-07-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1926c37beab16233dfc3ba3fa15fb622
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_817f6138b7321571b551d1ba3b81c029
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bdb512c383f33de025c1c01546d6fd09
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_93573df0bfb7ce6bb491e2c810a02575 |
| publicationDate |
2015-07-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9082846-B2 |
| titleOfInvention |
Integrated circuits with laterally diffused metal oxide semiconductor structures |
| abstract |
Integrated circuits with improved LDMOS structures are provided. An integrated circuit includes a semiconductor substrate, a plurality of shallow trench isolation (STI) regions, each extending at least a first depth below an upper surface of the semiconductor substrate. The STI regions electrically isolate devices fabricated in the semiconductor substrate. The integrated circuit further includes a transistor structure. The transistor structure includes a gate dielectric positioned over a portion of a first one of the plurality of STI regions, a drain region adjacent to the first one of the plurality of STI regions and spaced apart from the gate dielectric, a first gate electrode that extends over a first portion of the gate dielectric, a second gate electrode that extends over a second portion of the gate dielectric and positioned adjacent to the first gate electrode, and a source region positioned adjacent to the first portion of the gate dielectric. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10833164-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11393922-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11329153-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10269916-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10199475-B2 |
| priorityDate |
2013-04-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |