http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9059209-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66628 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66772 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-338 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 |
| filingDate | 2013-10-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2015-06-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9109b68b55594387713c374f294c46cb http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fe8eb8e3b1d12a84ac2f9be80f704730 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_33b0ef2dd4bd9622eb89f8bba4eda9ca http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6a5f69c3f59b08f18c724a24f7736558 |
| publicationDate | 2015-06-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-9059209-B2 |
| titleOfInvention | Replacement gate ETSOI with sharp junction |
| abstract | A method includes providing a silicon-on-insulator wafer (e.g., an ETSOI wafer); forming a sacrificial gate structure that overlies a sacrificial insulator layer; forming raised source/drains adjacent to the sacrificial gate structure; depositing an oxide layer that covers the raised source/drains and that surrounds the sacrificial gate structure; and removing the sacrificial gate structure leaving an opening that extends to the sacrificial insulator layer. The method further includes widening the opening so as to expose some of the raised source/drains, removing the sacrificial insulator layer and forming a spacer layer on sidewalls of the opening, the spacer layer covering only an upper portion of the exposed raised source/drains, and depositing a layer of gate dielectric material within the opening. A gate conductor is deposited within the opening. |
| priorityDate | 2011-08-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 43.