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filingDate 2007-07-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2015-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_36cbcbcc7ec5dbd8be69fff795fbd80d
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publicationDate 2015-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-8966488-B2
titleOfInvention Synchronising groups of threads with dedicated hardware logic
abstract The invention provides a processor comprising an execution unit arranged to execute multiple program threads, each thread comprising a sequence of instructions, and a plurality of synchronisers for synchronising threads. Each synchroniser is operable, in response to execution by the execution unit of one or more synchroniser association instructions, to associate with a group of at least two threads. Each synchroniser is also operable, when thus associated, to synchronise the threads of the group by pausing execution of a thread in the group pending a synchronisation point in another thread of that group.
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