| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B2207-094
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C2203-0742
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C2203-0714 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81B7-007
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1203
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C1-00246
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B81C1-00301 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 |
| filingDate |
2013-01-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2015-02-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6a12f3407d91e78d8b43c8a075fbe9aa
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3f2d84a5c5d379114bd5651e432563c0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_715ad765b4e535000bbd3c65a82c990e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_09cda1f2ababf5858ef26b82b13e54a3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2ce8d1fcb16d23719f959413b06f8082
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0e7a6d6806784e2f36ef855d2dd76039 |
| publicationDate |
2015-02-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8951893-B2 |
| titleOfInvention |
Fabricating polysilicon MOS devices and passive ESD devices |
| abstract |
A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11239369-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11271116-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10522686-B2 |
| priorityDate |
2013-01-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |