| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b0a6df6844944a1e86c15955ae218d12 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28079
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823857
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823864
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-338 |
| filingDate |
2012-11-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2014-09-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e7fe706d30bd4ebf8e6258a8ab85ed22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4c7717ab3e642c9dd5f7534e48bbd7a4 |
| publicationDate |
2014-09-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8828814-B2 |
| titleOfInvention |
Integrated semiconductor device and fabrication method |
| abstract |
A method is provided for fabricating an integrated semiconductor device. The method includes providing a semiconductor substrate having a first active region, a second active region and a plurality of isolation regions; forming a first gate dielectric layer on one surface of the semiconductor substrate; and forming a plurality of substituted gate electrodes, a layer of interlayer dielectric and sources/drains. The method also includes forming a first trench and a second trench; and covering the first gate dielectric layer on the bottom of the first trench. Further, the method includes removing the first dielectric layer on the bottom of the second trench; subsequently forming a second gate dielectric layer on the bottom of the second trench; and forming metal gates by filling the first trench and second trench using a high-K dielectric layer, followed by completely filling the first trench and the second trench using a gate metal layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10229931-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014349452-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10355139-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10115735-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9196542-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11217532-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10361213-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10615123-B2 |
| priorityDate |
2012-07-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |