| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_84a9afb8b730c7438bc2ce2137f1bf8a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_326a2b564321750bb00d969558d76317 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-2014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-346
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06G3-2014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06G2310-0221
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-147
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-2022
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2300-0857
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2300-0809
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0275
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0221 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G5-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-34 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-20 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F-
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G5-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-34 |
| filingDate |
2013-08-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2014-07-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6f81b356a0f2be91f5d193e24e9896fa |
| publicationDate |
2014-07-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8766887-B2 |
| titleOfInvention |
Allocating registers on a spatial light modulator |
| abstract |
Described is a device comprising: an array of light modulating elements; and one or more processing elements for controlling each of the light modulating elements, wherein the light modulating elements are arranged in a two-dimensional array, and wherein the one or more processing elements are adapted to skip some bit locations and use other bit locations of bit values when performing multiple bit logical and/or arithmetic operations. |
| priorityDate |
2003-05-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |