| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3c754156d9ab873a2efe5a3990dbf627 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6675
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1288
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1262
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-127
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-84 |
| filingDate |
2014-01-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2014-06-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ea5f5a88535b5e542f0dc6c162f267b1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_afca890b3b567f740b80bf5c9ad858eb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e5051558450e36e9b312c6bd2b934331
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0df3101644d613937e8aaee9c4d9c37a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c2c8bc0bfa67cef98936cf321a0cc415
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_40cc8b8f2f5a2f4cecb183d87464a6f5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b0bf6b2300650b2a53c95fe9b82e442e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a74645d7e2bbcb1d8078bb468db16230 |
| publicationDate |
2014-06-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8759165-B2 |
| titleOfInvention |
Manufacturing method of array substrate |
| abstract |
A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10665722-B2 |
| priorityDate |
2011-12-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |